De-synchronization is a process by which a synchronous circuit with one or more clock signals is transformed into a circuit where all clock signals are generated locally by a combination of asynchronous latch controllers, i.e. clock-less control circuits. The clock-less control circuits generate local clock signals and include delay elements or delay references, which model the circuit delay and timing depth of a combinational logic cloud. The delay elements also operate to regulate the local period of the clock-less control circuits.
A de-synchronized circuit, compared to its synchronous counterpart, presents several advantages, namely (i) post-silicon timing adaptivity to process, voltage and temperature variation, (ii) post-silicon voltage-controlled frequency tuning, (iii) lower electromagnetic emissions through appropriate skewing of the local de-synchronized clocks, (iv) non globally worst-case performance, as in the case of a synchronous circuit, as any timing margins from the typical process corner can be localized to particular circuit regions and integrated to their particular delay elements, thus avoiding global guard-banding.
A de-synchronized circuit typically requires the use of master and slave latches, instead of flip-flops, for sequential memory elements; this is due to the fact that there is skew present in the locally generated clocks. Any circuit with flip-flops requires zero, or very little timing skew between the clock signals driving the flip-flops. A de-synchronized circuit uses master and slave latches. A de-synchronized circuit generates two individual and independent master and slave clock signals, which operate as a replacement to the edge-triggered flip-flop clock. In this way, any skew between the local clocks can be arbitrary and correct flow of data can be imposed through the use of a data communication and synchronization mechanism, such as a handshake.
A de-synchronized circuit is composed of a number of de-synchronization regions, also referred to as de-synchronization partitions or de-synchronization register groups, whereby each such region (i) is driven by and controlled by a single asynchronous controller, which generates a common clock for all of the regions' sequential elements, and (ii) contains a single delay element per point-to-point connection with other regions. Observe that the de-synchronized circuit is asynchronous. Both terms are used interchangeably herein. Each delay element introduces an appropriate time delay, modeling the time delay of the combinational logic cloud present between each such point-to-point connection pair. The asynchronous controllers of the de-synchronization regions communicate with each other using an asynchronous handshake protocol, whereby each point-to-point connection assumes a request/acknowledgment signal pair. In the case of a many to one connection between de-synchronization regions, e.g. n-to-1, an n-input synchronization element, known as a C element or C gate must be used to generate a single request signal from the n available in order for the controller to wait for the last request signal to arrive. In the opposite case of a one to many connection between regions, e.g. 1-to-n, a C element must used to generate a single acknowledgment signal from the n available in order for the controller to wait for the last acknowledgment to arrive. Typically, the handshake protocol used is 2-phase in order to save on transitions on the handshake wires.
The transformation process of a synchronous circuit to a de-synchronized circuit does not offer a unique solution, but multiple, depending on the selection of de-synchronization regions and their number. However, no matter what the de-synchronized circuit, the flow of data through it will always be identical to the original data in the synchronous circuit, a property known as flow-equivalence.
Typically, the steps required to transform a synchronous circuit to a de-synchronized equivalent are the following:
(i) Manual specification of or automated derivation of the de-synchronization regions. This is a list of the sequential elements which belong to each de-synchronization region.
(ii) Conversion of the sequential elements of all de-synchronization regions into master and slave equivalents. Every flip-flop in every de-synchronization region is converted to a pair of master and slave latches with the same functionality and input and output signals. Typically, the master latch implements the equivalent flip-flop functionality, whereas the slave latch is an ordinary transparent latch with a single gate signal.
(iii) Insertion of asynchronous controllers generating the local clocks and delay-elements based on the data connectivity between regions. Each connection between regions requires a handshake pair, a single delay element, based on the timing depth of the combinational logic present between the regions, and potentially a synchronization element, at the sender and receiver for multiple input and output connections (e.g., the previously described C elements). Each controller outputs a local clock signal, which feeds all the sequential elements within its region. If the number of elements is large, it is necessary to buffer this signal using a low-skew buffer tree in a manner similar to a clock tree.
There are three significant drawbacks with conventional de-synchronization schemes: (i) the large number of delay elements required for m to n connections, which significantly impacts the area of the de-synchronized circuit, (ii) the timing mismatch between a delay element and its corresponding combinational logic cloud, and (iii) the rise/fall symmetry requirement stemming from 2-phase controller operation, transition time and buffering constraints for the delay elements.
Therefore, it would be desirable to provide techniques to address these drawbacks associated with conventional de-synchronization schemes.